[Integrated Inductors] Cutting-Edge Developments in On-Chip and MEMS Inductor Technologies

Basic Structure and Working Principles of Integrated Inductors

As electronic devices continue to evolve toward miniaturization and higher integration, traditional discrete inductors can no longer meet the requirements of System-on-Chip (SoC) and System-in-Package (SiP) solutions. Integrated inductors, as an emerging inductor technology, are gradually becoming key components in radio frequency integrated circuits and power management integrated circuits.

Definition and Classification of Integrated Inductors

Integrated inductors refer to inductive components manufactured directly on semiconductor chips or within packaging substrates, eliminating the need for external discrete components to achieve inductive functionality. Based on manufacturing processes and integration locations, integrated inductors are primarily classified into the following categories:

1. On-Chip Inductors:

• Manufactured directly on semiconductor chips using standard CMOS processes
• Utilize the chip's metal interconnect layers to form spiral or other conductor structures
• Fully integrated within the chip, requiring no additional packaging space

2. In-Package Inductors:

• Manufactured inside or on the surface of chip packaging substrates
• Utilize the metal layers of the packaging substrate to form inductive structures
• Packaged simultaneously with the chip, but not within the chip itself

3. MEMS Inductors:

• Manufactured using Micro-Electro-Mechanical Systems (MEMS) processes
• Can achieve three-dimensional and suspended structures
• Typically feature higher Q-factors and superior performance

4. Substrate-Embedded Inductors:

• Embedded within PCB or ceramic substrates
• Utilize the multi-layer structure of the substrate to form inductors
• Can achieve relatively large inductance values and higher power handling

Basic Structures of Integrated Inductors

The structural design of integrated inductors directly affects their performance parameters. Common integrated inductor structures include:

1. Planar Spiral Structures

Planar spiral structures are the most common form of integrated inductors, primarily including:

• Square Spirals:

• Simple structure, easy to manufacture

• Magnetic field concentration at corners, resulting in higher losses

• High space utilization efficiency

• Circular Spirals:

• Uniform magnetic field distribution, lower losses

• Higher manufacturing process complexity

• Q-factor typically higher than square spirals

• Octagonal Spirals:

• Combines advantages of both square and circular designs

• Easy to implement in standard CMOS processes

• Good balance between performance and area efficiency

• Polygonal Spirals:

• Number of sides can be optimized according to requirements

• Can achieve better performance for specific applications

2. Multi-Layer Stacked Structures

Multi-layer stacked structures utilize multiple metal layers of the chip or package to form three-dimensional inductor structures:

• Series Stacking:

• Multiple spiral inductor layers connected in series

• Can achieve larger inductance values

• Higher parasitic capacitance

• Parallel Stacking:

• Multiple spiral inductor layers connected in parallel

• Reduces DC resistance

• Suitable for high-current applications

• Symmetrical Stacking:

• Opposite spiral directions in upper and lower layers

• Reduces parasitic capacitance

• Improves self-resonant frequency

3. Suspended Structures

Suspended structures are primarily used in MEMS inductors, creating suspended conductor structures through microfabrication techniques:

• Suspended Spirals:

• Reduced coupling with the substrate

• Lower substrate losses

• Improved Q-factor

• Three-Dimensional Solenoids:

• Solenoid structures perpendicular to the chip surface

• Magnetic flux direction perpendicular to the substrate

• Reduced eddy current losses

• Toroidal Structures:

• Closed magnetic circuit, minimal magnetic field leakage

• Complex structure, difficult to manufacture

• Excellent EMI performance

Working Principles and Physical Mechanisms

The working principle of integrated inductors is identical to traditional inductors, based on Faraday's law of electromagnetic induction. However, due to their microscale dimensions and the unique integrated environment, their physical mechanisms have some distinctive characteristics.

1. Electromagnetic Induction Mechanism

When current flows through the conductor structure of an integrated inductor:

• A magnetic field is generated around the conductor, with magnetic flux density proportional to the current
• When the current changes, the magnetic field changes accordingly
• The changing magnetic field induces a counter-electromotive force in the conductor
• This counter-electromotive force opposes changes in current, manifesting as inductive characteristics

2. Loss Mechanisms

The loss mechanisms in integrated inductors are more complex than in traditional inductors:

• Conductor Losses:

• DC resistance losses (I²R)

• Skin effect losses (current concentration on conductor surface at high frequencies)

• Proximity effect losses (mutual influence of currents in adjacent conductors)

• Substrate Losses:

• Capacitive coupling losses (capacitive coupling between conductors and substrate)

• Eddy current losses (magnetic field inducing eddy currents in the substrate)

• Displacement current losses (alternating current through substrate capacitance)

• Radiation Losses:

• Electromagnetic wave radiation losses (significant at high frequencies)

• Related to inductor size and operating frequency

3. Equivalent Circuit Model

The equivalent circuit model for integrated inductors typically includes:

• Main inductance L: ideal inductance value
• Series resistance Rs: representing conductor losses
• Parallel capacitance Cp: representing inter-turn capacitance and ground capacitance
• Substrate capacitance Csub and substrate resistance Rsub: representing coupling with the substrate
• Mutual inductance M: representing magnetic coupling with surrounding circuits

These parameters collectively determine the performance characteristics of integrated inductors, including Q-factor, self-resonant frequency, and effective inductance value.

Design Challenges and Performance Limitations of On-Chip Inductors

On-chip inductors are inductive components manufactured directly on semiconductor chips. While they offer the advantage of high integration, they also face severe design challenges and performance limitations.

Fundamental Contradiction Between Size and Performance

The most fundamental challenge facing on-chip inductors is the contradiction between size and performance.

1. Relationship Between Inductance Value and Area

The inductance value of on-chip inductors is closely related to their occupied area:

• Approximate formula for planar spiral inductor inductance:
  L ≈ μ₀ × n² × davg × c₁ × ln(c₂/ρ)

Where:

• n is the number of turns

• davg is the average diameter

• c₁ and c₂ are shape-related constants

• ρ is the fill ratio (conductor width to spacing ratio)

• Area Efficiency Limitations:

• Inductance value is approximately proportional to area

• A 1nH inductor typically requires approximately 100μm×100μm area in standard CMOS processes

• Inductors larger than 10nH are extremely difficult to implement on-chip

2. Relationship Between Q-Factor and Size

The Q-factor is a key indicator for evaluating inductor performance, defined as the ratio of energy storage to energy loss:

Q = ωL/R

For on-chip inductors:

• Q-factor increases with inductor size
• Small-sized inductors typically have very low Q-factors (<10)
• Under the same process, Q-factor is approximately proportional to inductor diameter

Process Limitations and Challenges

Semiconductor manufacturing processes impose multiple limitations on on-chip inductor design.

1. Metal Layer Thickness Limitations

Metal interconnect layers in CMOS processes are typically very thin:

• Standard CMOS Processes:

• Regular metal layer thickness: 0.5~1μm

• Top metal layer thickness: 2~3μm

• Copper interconnects slightly thicker than aluminum interconnects

• Impact of Thickness on Performance:

• Thin metal layers result in high DC resistance

• Skin effect further increases effective resistance at high frequencies

• Limits the maximum current carrying capacity of the inductor

2. Metal Fill Density Rules

Modern CMOS processes require uniform metal fill density across layers to ensure planarity in chemical-mechanical polishing (CMP) processes:

• Typical Fill Density Requirements: 20%~80%
• Impact on Inductor Design:
• Need to add metal fill around inductors
• Metal fill creates parasitic coupling with the inductor
• Reduces Q-factor and alters inductance value

3. Design Rule Limitations

Semiconductor process design rules impose strict limitations on inductor structures:

• Minimum Line Width and Spacing:

• Limits the maximum number of turns per unit area

• Affects inductance value and Q-factor

• Metal Layer Spacing:

• Limits the performance of multi-layer stacked inductors

• Increases inter-layer parasitic capacitance

• Via Rules:

• Limits current density in inter-layer connections

• Increases series resistance